Content addressable memory (CAM) devices are often used in network switching and routing applications to determine forwarding destinations for data packets. A CAM device can be instructed to compare a selected portion of an incoming packet, typically a destination field within the packet header, with data values, called CAM words, stored in an associative storage array within the CAM device. If the destination field matches a CAM word, the CAM device generates a match address that identifies the location of the matching CAM word within the storage array, and asserts a match flag to signal the match. The match address is then typically used to address another storage array, either within or separate from the CAM device, to retrieve a destination address or other routing information for the packet.
The associative storage array of a CAM device, commonly referred to as a CAM array, is typically populated with CAM cells arranged in rows and columns. Precharged match lines are coupled to respective rows of the CAM cells, and bit line pairs and compare line pairs are coupled to respective columns of the CAM cells. Together, the bit line pairs form a data port for read/write access to address-selected rows of CAM cells, and the compare line pairs form a compare port for inputting comparand values to the CAM array during compare operations. The CAM cells themselves are specialized store-and-compare circuits each having a storage element to store a constituent bit of a CAM word and a compare circuit for comparing the stored bit with a comparand bit presented on the compare lines. In a typical arrangement, the compare circuits within the CAM cells of a given row are coupled in parallel to the match line for the row, with each compare circuit switchably forming a discharge path to discharge the match line if the stored bit and comparand bit do not match. By this arrangement if any one bit of a CAM word does not match the corresponding bit of the comparand value, the match line for the row is discharged to signal the mismatch condition. If all the bits of the CAM word match the corresponding bits of the comparand value, the match line remains in its precharged state to signal a match. Because a comparand value is presented to all the rows of CAM cells in each compare operation, a rapid, parallel search for a matching CAM word is performed.
FIG. 1 illustrates a row of CAM cells 101 within a prior-art CAM device 100. Each of the CAM cells 101 includes a pair of storage elements 115 and 117 to store data and mask bits (D and M), respectively, and a compare circuit 102 coupled to the storage elements and to a precharged match line, ML (i.e., precharged by precharge circuit, PC). The match line, in turn, is coupled to a match latch circuit 103 that includes a level-converting logic gate 105 and a latch element 107. Referring to FIG. 2, a compare strobe signal, CS, is asserted during a first cycle of a clock signal, CLK, to initiate a compare operation within the CAM device 100. At the following rising edge of the clock signal, a compare enable signal, CE, is asserted to enable a comparand value to be compared with CAM words stored within the CAM device, each bit of the comparand value being driven in complementary form onto a respective pair of compare lines coupled to a column of CAM cells 101. Within a given column of CAM cells, the compare line pair is coupled to gates of transistors 113a and 113b, respectively, of the compare circuits 102 (i.e., within each CAM cell of the column) to enable a comparison between the indicated comparand bit, C, and the data bit, D, stored within storage element 115 of the CAM cell. If the mask bit stored within storage element 117 is reset (i.e., M=0), then transistors 109a and 109b are switched on, enabling the compare circuit 102 to discharge the match line (and thereby signal a mismatch condition) if the data bit and comparand bit do not match. That is, if D=1 and C=0, then the transistor stack formed by transistors 109b, 111b and 113b is switched on to discharge the match line, and if D=0 and C=1, then the transistor stack formed by transistors 109a, 111a and 113a is switched on to discharge the match line. If the mask bit is set (establishing a mask or “don't care” state of the CAM cell), or if the data and comparand bits match, then at least one transistor in each transistor stack will be switched off, isolating the match line from ground within the CAM cell. If the comparand bits and data bits match (or are masked) within all the CAM cells of a row, then the match line will remain in its precharged state to signal the match condition.
Each of the match lines, ML, within the prior art CAM device 100 is discharged and charged according to the RC time constant established by the relatively high-capacitance of the match line and the resistance of the discharge path (i.e., one or more transistor stacks within the compare circuits 102 of a row of CAM cells 101). Referring to FIG. 2, a detect signal, DET, and latch signal, L, are asserted at the rising edge of the clock signal that follows assertion of the compare enable signal to latch the state of the match line, thereby providing one clock cycle for the match lines to be discharged during a compare operation. The detect signal is supplied to a first input of the logic gate 105 to enable the logic gate to output a logic-high or logic-low level match signal according to whether the match line has been discharged below a logic threshold (e.g., midway between logic high and logic low levels). The latch signal is provided to a latch enable input of the latch element 107 and, when asserted, enables the logic level match signal to pass through to the latch element output. When the latch signal is deasserted a short time later, the logic level match signal generated by the logic gate 105 is latched within the latch element 107. At this point, the compare enable signal is deasserted to enable the match lines to be precharged in preparation for a subsequent compare operation.
Still referring to FIGS. 1 and 2, the slowest match line discharge occurs when a single transistor stack discharges the entire match line (i.e., mismatch occurs in a single bit position of a comparand value). In that case, if one or more transistors within the transistor stack do not turn all the way on (e.g., due to a manufacturing defect), the match line is discharged more slowly due to the increased RC time constant and may not be sufficiently discharged by the time the detect and latch signals are asserted, potentially resulting in a false match indication being latched within the latch element 107. Wafer-level testing may identify such slow-discharge failures, with offending CAM rows (i.e., rows of CAM cells) being disabled and replaced by spare (redundant) CAM rows. If there are more defective CAM rows than spare rows, the device may be discarded prior to packaging to avoid the additional effort and cost of product finishing (i.e., packaging, testing, etc . . . ).
One limitation of many test systems is that the relatively high-inductance probes used to inject and measure signals make it difficult to replicate the full-speed operating environment of the CAM device. Referring to FIG. 2, for example, the clock frequency during waver-level testing is usually substantially slower than the clock frequency during normal device operation, resulting in a longer time for match line discharge before assertion of the detect and latch signals. Consequently, as shown in FIG. 3, detect signal assertion during wafer-level testing (DETWT) may occur after the match line level drops below a threshold level, resulting in a mismatch detection (i.e., passing the test), while detect signal assertion during normal operation (DETOP) occurs before the match line level drops below the threshold level, resulting in an undesired match detection (i.e., capturing a false match indication). Thus, a defective CAM row may go undetected during wafer-level testing resulting in wasted effort and expense to finish an ultimately defective device, the very result sought to be avoided by wafer-level testing. Although newer, higher speed test equipment may be used to detect slow-discharge CAM rows, such testers tend to be considerably more expensive than conventional testers and therefore drive up manufacturing cost.